DRAM memory arrays are formed of word lines (rows) and bit lines (columns) and memory cells located adjacent the intersections of the row and bit lines. Upon addressing a word line and a bit line, a memory cell coupled to the addressed word line and bit line can be written to or read from. To perform the addressing, address decoders decode address signals received from a memory controller and after decoding apply logic signals to row or column access field effect transistors.
Because memories sometimes have defects, it is common to include extra, redundant rows and columns to improve memory manufacturing yield. If a defect is found at one or more memory locations during testing, fusible links can be blown, e.g. by means of a laser beam, to eliminate the possible use of the defective rows or columns and substitute the redundant rows or columns in their place, thereby allowing the device to be used.
In large memories having very small geometric features, physical disconnection by the use of fusible links at each bit line or word line is difficult to achieve.